Conventionally, as general-purpose memories used in information processors such as computers or mobile communications devices, volatile memories such as DRAMs (Dynamic Random Access Memories) or SRAMs (Static RAMs) are used. Unless a current is always supplied to the memories, the volatile memories lose all information. Therefore, it is necessary to separately provide non-volatile memories for storing information, and as the non-volatile memories, flash EEPROMs (Electrically Erasable and Programmable ROMs), hard disk drives and the like are used. As information processing becomes faster, speeding up of the non-volatile memories is an important issue. Moreover, from another standpoint of recent development of information devices intended for so-called ubiquitous computing, the development of high-speed non-volatile memories as key devices has been strongly desired.
As an effective technique for the speeding up of the non-volatile memories, a MRAM (Magnetic Random Access Memory) is known. In the MRAM, each of memory cells arranged in a matrix form includes a magnetic device. A currently practical MRAM uses a giant magneto-resistive effect (GMR). The GMR is a phenomenon that in a laminate in which two ferromagnetic layers having easy magnetization axes oriented in the same direction are stacked, the resistance of the laminate is minimum in the case where the magnetization direction of each ferromagnetic layer is parallel to the easy magnetization axes, and is maximum in the case where the magnetization direction of each ferromagnetic layer is antiparallel to the easy magnetization axes. Each memory cell stores information of either of the two states corresponding to binary information “0” or “1”, and detects a difference in resistance corresponding to information as a change in current or voltage so as to read information. In an actual GMR device, two ferromagnetic layers are stacked with a non-magnetic layer in between, and the GMR device includes a fixed layer of which the magnetization direction is fixed, and a free layer (magnetic sensitive layer) of which the magnetization direction is changeable according to an external magnetic field.
Moreover, in a magnetic device using a tunneling magneto-resistive effect (TMR), the MR ratio can be much larger than that in the GMR device. The TMR is a phenomenon that in a laminate including two ferromagnetic layers (a fixed layer of which the magnetization direction is fixed and a magnetic sensitive layer of which the magnetization direction changeable, that is, a free layer) stacked with an insulating layer in between, the value of a tunnel current flowing through the insulating layer changes according to a relative angle between the magnetization directions of the two ferromagnetic layers. In other words, in the case where the magnetization directions are parallel to each other, the tunnel current is maximum (the resistance of the device is minimum), and in the case where the magnetization directions are antiparallel to each other, the tunnel current is minimum (the resistance of the device is maximum). As a specific example of the TMR device, a laminate structure of CoFe/Al oxide/CoFe is known, and its MR ratio is 40% or more. Moreover, the TMR device has high resistance, so it is considered that the TMR device easily matches a semiconductor device such as a MOS field effect transistor (MOSFET: Metal-Oxide-Semiconductor Field Effect Transistor). Such advantages allow a TMR-MRAM to achieve a higher output than the GMR-MRAM, so improvements in the memory capacity and the access speed of the TMR-MRAM are expected.
In both the GMR-MRAM and the TMR-MRAM, information is written in the same manner. More specifically, a current flows through a lead to induce a magnetic field, and the magnetization direction of the free layer is changed by the current magnetic field. Thereby, the relative magnetization directions of the ferromagnetic layers become parallel or antiparallel to each other, and corresponding binary information is stored.
For example, a TMR-MRAM in a related art has the following structure. As shown in FIG. 22, each write word line 202 (and each read word line 203) and each write/read bit line 201 are disposed so as to be orthogonal to each other. In this description, a line for writing is generically called write line. Moreover, a TMR device 207 is disposed between the write word line and the write/read bit line 201 in each intersection region to form each memory cell, although it is not shown. FIG. 23 shows a typical structure of the TMR device. Thus, the TMR device 207 includes a laminate which includes a first magnetic layer 204 as a fixed layer, a tunnel barrier layer 205 and a second magnetic layer 206 as a free layer. Moreover, the bit line 201 is disposed on one side of the laminate, and the read word line 203 and the write word line 202 are disposed on the opposite side of the laminate.
In the MRAM with such a structure, storing information in a memory cell means controlling the magnetization direction of the second magnetic layer 206 to a direction according to information. Information is stored in a target memory cell through flowing a current through a bit line 201 and a write word line 202 which are disposed so that the target memory cell is sandwiched therebetween. A magnetic field is induced by each current flowing through the write lines to generate a combined magnetic field, and the magnetization direction of the second magnetic layer 206 is changed by the combined magnetic field.
At this time, a write current is supplied to the write lines from a write current drive circuit (current drive). FIG. 24 shows an example of the structure of a current drive applied to a MRAM in a related art (refer to ISSCC 2000 Digest paper TA7.2). The circuit includes a portion for producing a pulse of which the shape is determined by a necessary write current value or the like and a portion for selecting a target write line to send the produced pulse to the selected write line. In this case, a reference signal generating portion 211, a positive amplifier 213A, a negative amplifier 213B, a current direction selecting portion 214, a timing block 216 and a pulse width controlling portion 217 correspond to the former portion. Further, a write line selecting portion 219 corresponds to the latter portion. The timing block 216 controls the timing of the pulse width controlling portion 217 as a time switch by a timing signal inputted into the write signal input line 215. The write line selecting portion 219 selects a write line where a pulse is supplied according to a decode signal inputted into an address decode line 218, and the write line selecting portion 219 typically includes a large number of switching devices each of which corresponds to each write line. An end of the write line is connected to the write line selecting portion 219, and the other end of the write line is grounded.
In the circuit, a data signal line 212 (Din) is branched, and at each branch of the data signal line 212, a positive amplification signal and a negative amplification signal are generated by the positive amplifier 213A and the negative amplifier 213B, and either of the positive amplification signal and the negative amplification signal is selected by the current direction selecting portion 214. Moreover, a reference signal is inputted into the positive amplifier 213A and the negative amplifier 213B from the reference signal generating portion 211 so as to adjust the magnitude of the inputted signal to a reference value. The data signal is a “High” or “Low” digital signal which represents data to be written, and in the circuit portion, for example, a “High” digital signal is simply amplified by the positive amplifier 213A, and a “Low” digital signal is inversely amplified to the pulse of a negative potential (that is, an amplified signal is selected), and as a result, either of a positive pulse and a negative pulse with a magnitude at a reference value is generated according to the data signal. The pulse is adjusted to a predetermined pulse width according to a necessary current amount in the pulse width controlling portion 217 to produce a write pulse. The write pulse is supplied to the write line according to the decode signal through the write line selecting portion 219. At this time, when a positive write pulse is applied to the write line, a current flows through the write line toward a ground side, and when a negative write pulse is applied, a current flows from the ground side to a pulse supply end.
Thus, conventionally, the shape and the sign of the pulse are adjusted so as to generate a write pulse which supplies a desired current amount to a predetermined direction of the write line, and the write pulse is supplied to the write line. FIG. 25A functionally shows such a current drive in a related art. A constant current control portion 300 represents a circuit element having a function of controlling the write current amount to a predetermined value in the above current drive including the reference signal generating portion 211 (in general, the height of a pulse cannot be controlled with high precision only by the reference signal generating portion 211, so a circuit for making a fine adjustment to a pulse voltage value is added).
However, in an actual MRAM, variations in the resistances of the write lines occur. The variations in resistance occur in the case where the lengths or the shapes of write lines vary depending upon the position of each write line or by a manufacturing error or the like. On the other hand, the current drive in the related art does not control the write current once supplied to the write line, so there is a problem that the amount of a current which actually flows varies from one write line to another according to the resistance. In other words, even if the current drive in the related art can control the write pulse with high precision, the current drive does not have a function of adjusting the supplied current amount according to the resistance of each write line, so an influence of resistance variations cannot be removed, and it is difficult to stably supply a constant current to the write lines.
In the MRAM, a magnetic field for write operation is a current magnetic field induced by a write current, so a write state (a magnetization state) in a device is determined by the magnitude of the magnetic field, that is, the magnitude of the write current. Therefore, in the case where the value of the write current is not constant, information cannot be stored in a stable state, or cannot be read out reliably, thereby it can be considered that it cause trouble in operation stability.
As a technique of controlling the supplied current amount according to the resistance of the write line, for example, it is considered that the current value is controlled to be constant on the downstream side of the write current, thereby the current amount which flows through the whole write line can be constant. In other words, as shown in FIG. 25B, the constant current controlling portion 300 is disposed on the ground side of the write line. However, a typical constant current circuit is a circuit using a band gap reference which includes a transistor, a diode or the like, so in this case, the current direction is limited to one direction, so a current cannot flow through one write line in both directions. When a current flows in both directions in the write circuit system, as shown in FIG. 25C, two write lines are bundled, and it is necessary to symmetrically dispose circuit systems. However, it is not impractical, because the circuit structure and the control become complicated. In the current drive of the MRAM, it can be said that controlling the write current in both directions is an indispensable condition, and a task of controlling the write current to a constant value must be accomplished while satisfying the condition. However, as described above, it is not easy to achieve a circuit which satisfies the condition and accomplishes the task, and an effective problem-solving technique has not been proposed.
Moreover, it can be considered that a constant current circuit is disposed in each current drive corresponding to each write line. However, when each current drive independently has the constant current circuit, the power consumption is increased, and variations in a current flowing through each write line may be increased. Moreover, when the constant current circuit is disposed in each current drive, the number of circuit components is increased.